Integrated circuits which perform logic functions provide digital logic signals at their output. In order to provide a transmission signal and to isolate the circuit logic elements from external interference, an output driver or buffer is typically employed. The output driver is connected between the logic circuit and transmission line and is usually fabricated on the same chip as the logic circuit. The driver responds to a data signal from the logic elements on the chip and provides a corresponding output signal on the transmission line. One type of output driver utilizes a single transistor connected between the transmission line and a reference voltage terminal. The transmission line is precharged to a high or low voltage corresponding to a high or low logic level. The output driver transmits a complementary signal by connecting the line to a reference potential terminal having a complementary value of the precharged line. A common driver configuration is an NMOS field effect transistor connected between the transmission line and ground with the transmission line precharged to a high value. This so-called "open drain driver" derives its name from the connection of the NMOS drain to the transmission line. When a low value is to be transmitted, the gate of the NMOS transistor receives a signal from the logic circuit creating a conduction path to ground and pulling the transmission line low.
Output drivers are known to have several problems associated with their operation. In some applications the transmission line has an effective external load with a significant capacitive component. When the driver transistor conducts, this capacitive effect can result in an excessive instantaneous current or spike through the transistor. In addition, in many circuits the switching speed of the driver transistor has evolved to the point where the time rate of change of the current has significantly increased. This can result in excessive noise in the power supply. Since the power supply is also connected to the chip, disturbances in the power supply voltage can upset the operation of the chip.
In gate array and other ASIC applications the loading of the transmission line is frequently unknown. Typically, a maximum source or sink current is specified. However, the capacitive effect is unknown and may vary over a relatively large range of values. Many output drivers operate well within a narrowly defined operating range but are not equipped to handle variable transmission line loading.